The quantity of functions incorporated on a semiconductor integrated circuit chip has dramatically increased over the years to such an extent that system designers are able to put entire systems on one integrated chip. These systems include both complex analog and digital circuits. As the level of complexity increases, the ability to provide reliable and comprehensive testing of the system on the chip also becomes difficult. Although improvements have been made in the testing of digital circuits and in the use of techniques which employ sigma-delta modulators to monitor direct current voltages on the chip, similar advancements have not been achieved in the testing of analog circuits.
Comprehensive testing of analog circuits equates to having the ability to monitor the internal nodes of the circuit on the chip. This is supported by the fact that some outputs do not necessarily change in response to a test signal. Therefore, it is generally important to test signal levels at these internal nodes. Prior art methods for testing internal nodes included routing the internal nodes off chip and monitoring them externally. Such prior art methods further include using analog shift registers or charged coupled devices to implement scan testing, where scan testing is defined by the shifting or scanning of a test signal or pattern through the system under test and producing a signature indicating proper or faulty operation of the circuit. One method of providing a test signal uses a sigma-delta modulator digital-to-analog converter to produce analog test signals from digital test signals stored on the chip.
Referring to FIG. 1, there is shown a prior art structure 100 for testing an analog circuit 105. Analog circuit 105 includes serially connected operational amplifiers 110. Output lines 112 from operational amplifiers 110 are routed to an internal analog multiplexer 115, which selectively provides one of the output lines 112 to a buffer amplifier 120 in response to a signal from a digital controller. The buffer amplifier analog output 130 is then routed off chip for testing via external analog test equipment.
Referring to FIG. 2, there is shown a prior art structure 200 for testing analog circuit 205 using a scan testing implementation. As before, analog circuit 200 includes serially connected operational amplifiers 210. In this scheme, a digital clock signal 215 clocks in an analog test signal 220 through a set of serially connected analog shift registers 230 and clocks out an analog output signal 240, which is fed to a buffer amplifier 250. The buffer amplifier analog output 260 is then again routed off chip for testing via external analog test equipment.
Each of the above mentioned techniques has several disadvantages. For example, an internal analog multiplexer circuit has to be used to route the internal nodes off chip, since there are a limited number of output pins. During the testing operation, the analog multiplexer circuit loads the analog circuit under test, thereby effecting the characteristics of the signal being tested. As such, this requires the utilization of a buffer amplifier to provide isolation. The prior art methods also require routing the analog test signals internally and off chip, and that the test signal be able to drive external analog testing equipment, which in turn increases the cost of the testing. In other prior art schemes, an internal analog-to-digital converter is utilized. This implementation has the added drawback of consuming generally large areas of valuable semiconductor area, which could be utilized for additional circuitry.
Accordingly, there is a need to provide an apparatus and method which overcomes the above disadvantages of the prior art, but still provides comprehensive and reliable testing of the analog circuits.